芯片制造工艺问答005：Well制程影响那些组件特性?
Ans Well表面的Dopant浓度会影响：Vt、Id、Source / Drain Capacitance and Field isolation。Well中部的Dopant浓度会影响：Punch-through。Source, Drain breakdown voltageWell底部的Dopant浓度会影响：Latch-up and Well junction breakdown volt
技术问答
芯片制造工艺问答017：黄光区曝光机共有几种机型? 他们各别有什么任务? 试列表比较其特性?
Ans FAB5 PHO area have 8 EQ model (the information
should be updated according to E3PHO) as attached table:I- line stepper: Default lithographerI- line scanner: for better uniformity and
larger field
芯片制造工艺问答020：总共有多少种光阻去除方式? 个别适用于何种情况?
Ans For FAB* stripping process, clear functions layout
are designed by machines & process layers, which are simply described as
below:(1)Dry ashing:M/CTotal recipe
No.Function designProcess laye
芯片制造工艺问答015：STI蚀刻后需检查什么地方以确保蚀刻正常? 这些项目在密集区何疏散区有何不同?
Ans 检查trench
edge, SIN AEI, at high pattern density region, STI profile is more steep,
profile deeper, SIN AEI smaller; at lower density region, STI profile less
steep, SIN AEI larger. 需检查Test
pattern
芯片制造工艺问答016：Active PHO (OD PHO)需检查什么以确保制程正确无误?
Ans 1. ADI
CD: because the low reflectivity property of SIN film, the CD uniformity within
a wafer is usually not so good, depends on PR thickness and SIN thickness, the
CD will be smaller in wa
芯片制造工艺问答012：Pre-Clean的目的为何? 目前共有几种Pre-Clean recipe存在FAB内? 个别的目的有何不同?
Ans Pre-Clean 一般指 Pre furnace/RTP clean.Presently active Pre-clean have 22 recipes; while
dilute APM 1 recipe(see attach file: clean.xls) Pre-clean 为SPM,APM,HPM,HF 依个别需求调整使用时间之clean process, SPM is fo
芯片制造工艺问答007：何谓LOCOS? Typical process flow?
LOCOS 为Local Oxidation 的简称在先进的集成电路制程中，可以在面积的硅表面上挤进多达数十万的MOS晶体管，为了使晶体管与晶体管间的操作不受到对方的干扰，必需将每个集成电路上的晶体管，与其它的晶体管相隔离，避免产生短路。在0.25
um制程之前，LOCOS是被普遍使用的绝缘隔离制程，因为它非常简单。以下为0.30
UM TPDM SRAM Technology LOCOS pro
芯片制造工艺问答008：何谓STI? Typical process flow?
Ans STI 为Shallow Trench Isolation的简称在0.25
um制程之后，STI是标准的绝缘隔离制程。以下为0.25 UM LOGIC
Technology STI process 的简述PAD OXIDE (920C, 110A) ,因SIN与SI间的应力很大，需要一层OXIDE做为缓冲。SIN D
芯片制造工艺问答011：ODR pattern density对STI CMP有何影响?
Ans ODR density愈高，CMP的etch
rate会愈快，且ODR density也与STI density相关(STI density高，OD
density就低，相对地ODR density也要增加)Polish amount simulation equation by E2CMP (KA) =
[OD_ mask_field_ratio x (1- ODR_mask_field
芯片制造工艺问答010：何谓ODR? 对产品有何影响?
Ans 如第8题的附图，在STI-HDP OXIDE Deposition后，Trench密集区的OXIDE多填入Trench内，而空旷区的OXIDE多在SIN之上，如此在后续的CMP制程将会引致不同的Polishing rate。因此用一个OD Reverse Tone(简单来看就是一个和OD Pattern相反的光罩)将空旷区的OXIDE曝开再由OXIDE ETCH将在SIN上的OXIDE吃掉
