芯片制造工艺问答037：PHO recipe的Focus设定值往正"+"调整后PR profile会有何影响?
Ans positive: 往正调整会造成所谓的”削头”的情形,如下图所示 negative:往负调整会造成所谓的”解不开”的情形,如下图所示
技术问答
芯片制造工艺问答036：PHO Overlay shift的原因及现象有哪些? 其中有多少种可以经由给机台补偿改善?
Ans (1) phenomenon:translation, rotation and magnitude, trapezoid, tilt (2) reason: as belowtabler 平移 旋转 水平 扭曲 倍率 X, Y large mean, small range
芯片制造工艺问答035： Lot to lot, within lot wafer to wafer, within wafer, within field.
Ans (1) lot to lot :不同lot之间的差异性, due to EQ, material, environmental shift(2) within lot waferto wafer:同一个lot中,不同wafer之间的差异性, due to batch run conditional shift. E.g. Lensheating, CVD film thicknes
芯片制造工艺问答034：解释名词, PHO proximity effect, Swing effect, Exposure latitude, Best Focus.
Ans Pho proximity effect: (近接效应)Optical proximity effect is a nature result of the optical interference,diffraction effects. Because diffraction nature of incident lights, it’simpossible to elimin
芯片制造工艺问答033：说明Gate oxide quality (integrity)如何量度? 解释不同方法的优缺点 (Vbd, Qbd, )
Ans Vbd: pattern 2000×2000um2, die no=72ea, Vbd>= 8V for oxidethickness 70A, Vbd>=12V for oxide thickness 115A. Vbd>=6.5V, pass orVbd<=2.5V, mode A failure, 2.5V < Vbd< 6.5V, B mo
芯片制造工艺问答031：Gate oxide厚度如何Monitor? 其量测误差为何? 在线如何控制厚度保持定值?
Ans Gate oxide厚度Monitor: 每个RUN需将控片(C/W)与产品芯片一起进炉管, 控片(C/W)分别摆放在上, 中, 下位置. 在oxidegrowth后以椭圆测厚仪(ellipsometer)测量thin oxide thickness.Within wafer uniformity: (芯片内九点之MAX-MIN) / (2×九点之平均值)Wafer to wafe
芯片制造工艺问答030：Gate oxide 前制程B-Clean的目的为何? 其中的APM dip time会影响什么产品参数?
Ans Remove Si surface particles, metal Ion, organic,micro-roughness and native Oxide. --> Use 22220A,where SPM (CR) 1min to remove light organic, 100:1 HF 3min to remove any nativeoxide, and AP
芯片制造工艺问答029：Gate oxide 成长有哪些重要考虑?
Ans 降低成长速率以利厚度均匀度控制 --> 采用dry oxide, or low flow rate/temperature wetoxide. 温度随产品技术演进而降低使用Cl-离子growth, etch方式, 减少金属污染. --> 采用合乎环保的Trans-LC作为Cl离子来源低温出炉, 以降低Si/SiO2的oxide fixed charge density.
